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Technical Program
Paper Detail
| Paper: | WP-P7.2 |
| Session: | Implementation of Image & Video Processing Systems |
| Time: | Wednesday, October 11, 14:20 - 17:00 |
| Presentation: |
Poster
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| Title: |
FPGA ARCHITECTURE FOR REAL-TIME VIDEO NOISE ESTIMATION |
| Authors: |
Francois-Xavier Lapalme; Concordia University | | | | | Aishy Amer; Concordia University | | | | | Chunyan Wang; Concordia University | | |
| Abstract: |
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives of this work consist of adapting a computationally demanding noise estimation algorithm to a synthesizable VHDL design and achieving real-time performance. This method uses a block-based technique that considers image structure to find intensity-homogeneous blocks. Subsequently, these blocks are included in the averaging process to estimate the noise variance. Generating worst-case estimation error of 3 dB, this spatial noise reduction method is reliable for highly noisy and textured images. The proposed architecture provides a satisfactory compromise between area and processing speed. Furthermore, parameterization of the architecture allows additional flexibility with the scaling of mask sizes that can operate on 3x3 or 5x5 blocks of pixels. The proposed design is targeted to an FPGA device and estimates the noise variance over a 720x480 interlaced PAL video sequence using 8 bit gray-scale pixel data. |
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