 |
Technical Program
Paper Detail
| Paper: | TP-P8.1 |
| Session: | Multiresolution Processing |
| Time: | Tuesday, October 10, 14:20 - 17:00 |
| Presentation: |
Poster
|
| Title: |
EFFICIENT LINE-BASED VLSI ARCHITECTURE FOR 2-D LIFTING DWT |
| Authors: |
Keyan Wang; Xidian University | | | | | Chengke Wu; Xidian University | | | | | Kai Liu; Xidian University | | | | | Yunsong Li; Xidian University | | | | | Jechang Jeong; Hanyang University | | |
| Abstract: |
DWT has been the basis of image compression, such as in JPEG2000. This paper proposes a novel VLSI architecture that performs line-based DWT using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. The intermediate buffer is composed of FIFOs to store temporary results of horizontal filters. The control module schedules the output of wavelet coefficients to external memory with the priority from high to low. Horizontal filtering and vertical filtering are simultaneous, and all levels of DWT are processed parallel. The presented architecture finishes multi levels of 9/7 DWT in one image transmission time. Meanwhile, it decreases significantly memory used and hardware resource required. This architecture is suitable for various real-time image/video applications. |
|
