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My ICIP 2006 Schedule
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Paper Detail
| Paper: | WP-P7.7 |
| Session: | Implementation of Image & Video Processing Systems |
| Time: | Wednesday, October 11, 14:20 - 17:00 |
| Presentation: |
Poster |
| Topic: |
Implementation of Image & Video Processing Systems: Embedded and real-time systems |
| Title: |
ANALYSIS AND OPTIMIZATION OF UB VIDEO'S H.264 BASELINE ENCODER IMPLEMENTATION ON TEXAS INSTRUMENTS' TMS320DM642 DSP |
| Authors: |
Imen Werda; ENIS | | | | | Faouzi Kossentini; UBVideo | | | | | Mohamed Ali Ben Ayed; ENIS | | | | | Nouri Massmoudi; ENIS | | |
| Abstract: |
The high coding efficiency enabled by the H.264 standard comes with substantially greater algorithmic complexity as compared to that of existing standards. This additional complexity complicates very much the implementation and optimization tasks. However, efficient implementations on different platforms exist that achieve real-time constraints in several video applications. One such good example is UB Video’s implementation of an H.264 Baseline encoder on the Texas Instruments’ TMS320DM642 (DM642) Digital Signal Processor, which can achieve good speed-quality trade-offs in video conferencing applications. In this work, we analyze and optimize UB Video’s implementation of its H.264 Baseline encoder on the DM642. As a result, we have been able to improve memory transfer efficiency and reduce execution time, reducing the total number of encoder cycles by 18% without any loss in video quality. |
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